

-- @module : Controller_tb
-- @author : ben


library ieee;
use ieee.std_logic_1164.all;

entity Controller_tb is 
end Controller_tb;     
        

architecture rtl of Controller_tb is

component Controller port (
    clk	: in bit;
    loadM : in bit;
    loadQ : in bit;
    start : in bit;
    reset : in bit;
    Q_zero : in bit;
    Q_prev : in bit;
    counter_overflow : in bit;
    
    clear : out bit;
    done : out bit;
    M_load : out bit;
    Q_load : out bit;
    A_hold : out bit;
    Q_hold : out bit;
    Q_Prev_hold : out bit;
    add_notSub : out bit;
    counter_en : out bit
    );
end component;        

for all : controller use entity work.Controller;

	signal clk	: bit := '0';
    signal loadM : bit;
    signal loadQ : bit;
    signal start : bit;
    signal reset : bit := '0';
    signal Q_zero : bit := '1';
    signal Q_prev : bit := '0';
    signal counter_overflow : bit;
    
    signal clear : bit;
    signal done : bit;
    signal M_load : bit;
    signal Q_load : bit;
    signal A_hold : bit;
    signal Q_hold : bit;
    signal Q_Prev_hold : bit;
    signal add_notSub : bit;
    signal counter_en : bit;
    
    signal M_DATA : bit_vector(31 downto 0) := "00000000000000000000000000000000";
    signal Q_DATA : bit_vector(31 downto 0) := "00000000000000000000000000000001";


begin  

clk <= not clk after 25 ns;

UUT : Controller port map (
		
	clk,
    loadM,
    loadQ,
    start,
    reset,
    Q_zero,
    Q_prev,
    counter_overflow,
    
    clear,
    done,
    M_load,
    Q_load,
    A_hold,
    Q_hold,
    Q_Prev_hold,
    add_notSub,
    counter_en

		);
		
	loadM <= '1' after 100 ns, '0' after 150 ns, '1' after 4.1 us;
	loadQ <= '1' after 250 ns, '0' after 300 ns;
	start <= '1' after 400 ns, '0' after 450 ns;
	
	counter_overflow <= '1' after 2 us;
	
	reset <= '1' after 3 us, '0' after 4 us;

end rtl;








